The present invention relates generally to logic analyzers used in measurement of data in digital data switching systems, such as routers, switches and hubs that carry communication data on parallel buses, and more particularly to user interfaces and to configuring a logic analyzer to trigger on data communications packets and constructs within selected protocols.
As known by those skilled in the art, a logic analyzer is an electronic instrument used to detect, analyze, and display digital signals. Logic analyzers are commonly used to debug the internal operation of digital data switching systems such as routers, switches, and hubs. These digital data switching systems carry communication data on parallel buses. Inside the switching systems, a commercial network or protocol analyzer is of no use, as the protocols used internally are often non-standard, and the buses cannot be connected to the network interfaces of protocol analyzers.
Logic analyzers are digital data acquisition instruments that allow an operator to acquire and display digital signal data from a large number of logic signals, such as those that travel over address, data and control lines of a device under test (xe2x80x9cDUTxe2x80x9d). A device under test may include one or more separately packaged devices such as those noted above as well as other circuits and devices.
The logic signals are acquired from the device under test on hardwired lines referred to as channels. The channels may be physically assembled into groups commonly referred to as pods. The received signals are sampled and digitized to form signal data. Digitizing typically includes comparing a voltage magnitude of each logic signal sample to a reference voltage to determine the logical state of the signal. Sampling may occur at one of a number of selectable rates, depending on the frequency at which the sampled signals change logic states. The resultant signal data are stored, under the control of a sampling clock, in a signal data memory generally having a fixed size. The data are typically stored sequentially such that consecutive signal samples are stored in consecutive memory locations. Due to the quantity of signal data, signal data memory is commonly implemented as a wrap-around buffer.
Selection of the signal data to be subsequently presented on a display is determined by an operator-defined trigger specification. The trigger specification (also referred to as a trigger set-up) is specified generally by a trigger definition, and a number of parameters collectively referred to as trigger control parameters or, simply, trigger controls. The trigger definition identifies the occurrences that result in signal data being stored.
A trigger definition, which may be a trigger sequence, is comprised of one or more trigger sequence levels. Each sequence level may include any number of trigger branches, each of which sets forth a branch condition that causes the logic analyzer to execute the action defined in that trigger branch. Such execution results in the storage of signal data or further processing of a subsequent sequence level. The final branch condition that causes the acquisition of signal data is commonly referred to as a trigger condition.
Branch conditions are specified by the occurrence of one or more events. An event is defined as an occurrence of certain characteristics or properties of a signal, such as a rising or falling edge of a signal, a logic high or logic low signal state, etc. Events may also be defined based on internal resources, such as internal timers, counters, etc. Typically, a branch condition specifies a number of events that occur simultaneously or in a relative time sequence.
After the trigger specification is specified, the operator can perform a measurement, that is, initiate acquisition of signal samples. When signal data capture is initiated, the signal data is compared to the specified trigger definition. When the trigger definition is satisfied, the signal data is captured in accordance with the specified trigger controls and stored in signal data memory. Subsequently, the signal data memory may be sequentially accessed and the signal data memory displayed.
Constructing a trigger definition can be very complicated and time consuming. Conventionally, trigger definitions are expressed in esoteric trigger programming language. Learning such a programming language is often difficult and inconvenient. However, even with such proficiency and knowledge, formulation of even simple trigger definitions still requires considerable time and effort due to the complexity of the programming language. In other words, such programming languages, although suited for development of complicated trigger definitions, are burdensome to developing simple and complicated trigger definitions alike.
Logic analyzers provide many configuration functions as a result of the increasing operational complexity of target devices. In many measurement applications, however, not all of the configuration functions are needed to obtain simple measurements, that is, the necessary configuration functions are selected in accordance with the level of measurement complexity. Also, the complexity involved in configuring a logic analyzer to properly trigger on a desired communications packet or protocol leads to uncertainty. There are many different ways a user could incorrectly configure the trigger setup, thus leading to doubts as to whether the event being sought for analysis actually happened, or whether the logic analyzer is configured incorrectly.
Conventional logic analyzers include a graphical user interface that allows a user to make selections with respect to the configuration functions. In prior art logic analyzers, the user is required to make selections with respect to all the configuration functions, even if the desired measurements do not require some of the configuration functions. In prior art logic analyzers, trigger configuration displays generally have a setup window and a number of selectable tabs such as: a sampling tab; a format tab; a trigger tab; and a symbol tab. Selection of the trigger tab causes the typical graphical user interface to display a trigger sequence selected by the user. As an example, the user can configure the logic analyzer to trigger when an Internet Protocol packet destined for the IP address 15.19.4.195 crosses the particular bus then being probed. The process requires the user to program the logic analyzer using a sequence of trigger primitives. Each portion of the trigger sequence must be manually constructed by the user. The trigger sequence contains many steps. The first primitive requires the user to configure the first part of the trigger to recognize the Start of Packet bit in a data stream, then, step 2 will be sequenced. Primitive 2 requires the user to set the configuration so that the logic analyzer will look at a specific number of clock cycles and then go to primitive 3 regardless of the content. This requires the user to have intimate knowledge of the construction of data protocols and, accordingly, to know how many clock cycles will occur before data of import to the specific sequence of interest will occur. In the next primitive, the user must set the configuration so that if a particular value occurs on the bus for a predetermined number of times, then sequence will step to the next primitive, otherwise the sequence will start over at primitive 1. The process of constructing individual primitive continues until the user has constructed a sequence to trigger on exactly the desired protocol construct for IP address 15.19.4.195.
In the above example, it is noteworthy that the user must also make mental conversions from the hex representations of the IP address to the digital representation. IP addresses are commonly represented as a series of decimal coded hex numbers, such as 15.19.3.116. In the above example, the hex numbers 0F13 0374 must be mentally converted to the digitalxe2x80x9415.19.3.116.
These necessary configuration function-setting operations are time-consuming and increase the possibility of error in setting the trigger configuration. There are numerous ways in a user could incorrectly configure the trigger setup, leading to doubt as to whether the event being sought actually happened, or if the logic analyzer is simply mis-configured. The complex array of configuration settings renders the setup of the logic analyzer confusing to unskilled or unfamiliar users of the logic analyzer.
The present invention is a system and method for configuring a logic analyzer to trigger on data communications packets and constructs within selected protocols. The present invention is useful for debugging data flow on a communication bus (such as ATM or Ethernet) or any other bus with a communication protocol (such as PCI). The present invention is useful in converting the constructs within selected into a trigger sequence.
In accordance with the invention, a system and method is provided whereby the normally complex array of configuration settings necessary for a logic analyzer trigger definition is simplified. Protocol definitions are created and stored in a shared database. The protocol definitions are parsed into data structures for each particular protocol. The data structures are then used by a trigger mechanism to create two blocks of dataxe2x80x94a data bit block and a xe2x80x9cdon""t carexe2x80x9d mask block. This pair of bit blocks is stored in memory. Together, this bit block pair comprises an event definition.
Once the event definition is stored, it can be used to create a logic analyzer trigger definition. A trigger definition is comprised of one or more trigger functions. Each trigger function is a graphical representation of an underlying one or more trigger primitives. A trigger primitive is translated into a form suitable for controlling the signal measurement system. Trigger primitives comprise one or more trigger branches used to form a sequence level of the trigger definition. For a selected trigger function, either the trigger function or its underlying trigger primitives are displayed in a trigger definition region of the display window for editing by the operator.
In one aspect of the invention, a user configures a logic analyzer trigger sequence by using an event editor. The event editor is presented to the user in a graphical user interface that allows the user to use protocol definitions to describe an event of interest. The logic analyzer converts the event of interest selected by the user into a series of primitives. This series of primitives results in a trigger sequence used by the logic analyzer to capture and store bus data.
Various embodiments of the present invention provide certain advantages and overcome certain drawbacks of the conventional techniques. Not all embodiments of the invention share the same advantages and those that do may not share them under all circumstances. Further features and advantages of the present invention as well as the structure and operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the drawings, like reference numerals indicate identical or functionally similar elements.